The present invention is directed, in general, to a method of semiconductor fabrication and, more specifically, to a method of manufacturing an interconnect structure within a substrate employing a passivation layer to inhibit the diffusion of elements from the substrate.
In the fabrication of advanced very large scale integration circuits (VLSI), Deep ultra-violet (DUV) lithography is widely used. Low dielectric constant (low k) inter-metal dielectrics are used in order to improve performance by reducing parasitic capacitance. Copper interconnects, which improve performance due to copper""s low resistance, have also recently gained wide acceptance. These copper interconnects are typically formed using damascene or dual damascene processes to define the interconnect paths, and are typically used in conjunction with porous dielectric materials that have low dielectric constants (low k).
One approach of the damascene process is a full via first approach, which provides lower cost processing, improved level-level alignment tolerance and thus tighter design rules and improved performance. In the full via first approach, via holes are etched first, and then the trench is etched. The full via first is etched down to the copper or previous a layer of dielectric using the dual damascene process.
One problem associated with the full via first dual damascene approach is its integration with chemically amplified DUV photo resist (PR) systems. Because etch selectivity is needed when etching the via, nitrogen is added to the chemistry. However, the added nitrogen, in its radical form, diffuses into the porous, low k material. When trench lithography is performed, a DUV photoresist is put down into the via. The photoresist contains photo acid generators that are activated by DUV, thus forming photo acid catalysts. The photo acid catalysts, in turn, work to break the bonds of the photoresist, the photoresist then becomes soluble amino groups (weak base) that were previously lodged in the porous low k material freely leach out into the photoresist and interact with the photo acid catalyst (weak acid) and renders the photo acid catalyst inactive. This, in turn, prevents the photoresist from developing properly, which results in unwanted dome-like features, which cannot easily be removed.
Previous attempts to prevent the formation feature anomalies during trench lithography involves use of a DUV resists that are less sensitive to the basic amide groups of the low k material. Unfortunately, however, these alternate photo resist systems sacrifice feature size and resolution. This sacrifice in feature size and resolution is unacceptable because the success of semiconductor devices, especially those that pertain to computer and telecommunications applications, depends on both high speed operation and smaller device size, which require a high degree of resolution in the manufacturing process. Another attempt to prevent formation feature anomalies during trench lithography is to use a thick bottom anti-reflective coating (BARC) to passivate the service. Although a thicker BARC layer alleviates feature anomalies, it fails to eliminate the problem completely.
Accordingly, what is needed in the art is a method of manufacturing a semiconductor device that overcomes the deficiencies of the prior art.
To address the above-discussed deficiencies of the prior art, the present invention provides a method of manufacturing an interconnect structure within a substrate. In an advantageous embodiment, the method includes forming an opening in a substrate. In one aspect of this particular embodiment, the substrate may be a dielectric layer having a low dielectric constant; for example, one where the dielectric constant ranges from about 3.9 to about 1.9. This particular embodiment further includes forming a passivation layer within the opening and a photoresist within the opening and over the passivation layer. The passivation layer inhibits the diffusion of elements from the substrate that can deactivate a photo acid generator (PAG) within the photoresist, which inhibits the photoresist from developing properly. Due to the presence of the passivation layer, the photoresist is able to develop properly, which prevents the formation of photoresist anomalies, as found in prior art process. Thus, the presence of the passivation layer addresses the problems associated with the above-discussed prior art processes.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.